Flip-Flop, Complementary Output, Positive Edge, 74LVC1G74, D, 280 MHz, 50 mA, TSSOP - 

74LVC1G74DP,125 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (active-low SD) and reset (active-low RD) inputs, and complementary Q and active-low Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as translator in mixed 3.3V and 5V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.