High Speed CMOS Logic Dual Negative Edge Triggered JK Flip Flops with Set and Reset, 14ns, 60MHz - 

The CD74HCT112E is a dual negative-edge-triggered J-K Flip-flop with set and reset. It utilizes silicon-gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. It exhibits the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. It has independent J, K, Set, Reset and Clock inputs and Q and Q\ outputs. It changes state on the negative-going transition of the clock pulse. Set and Reset are accomplished asynchronously by low-level inputs. The HCT logic family is functionally as well as pin-compatible with the standard LS logic family.